Complex ASICs are designed using a variety of CAD tools. One such tool is an HDL circuit simulator for circuits represented by a list of statements in a Hardware Description Language (HDL), such as Verilog or VHDL. The HDL circuit simulator is used to simulate and debug a specified data processing circuit. Typically the HDL description of the circuit is simulated and revised until the circuit designer is satisfied that the specified circuit would work properly.
The object of the present invention is to provide an ASIC synthesizer that synthesizes a circuit netlist from an HDL circuit description using a library of datapath circuit elements (i.e., circuit elements with formal HDL circuit descriptions) and a library of gate elements. A netlist comprises a list of circuit components and the interconnections between those components. Once a netlist has been generated, there are a number of commercially available "silicon compilers", sometimes called "datapath compilers" or "place and route tools," that may then be used to convert the netlist into a semiconductor circuit layout, using a layout cell library of defined circuit elements, or to convert the netlist into a set of interconnections in a gate array. Other CAD tools (such as the COMPASS QTV) may then be used to verify that the resulting circuit layout will, in fact, meet timing requirements or other constraints for the specified circuit.
A primary problem with prior art datapath synthesizers is that the description of the datapath library of elements, used to match HDL statements in the HDL circuit description, have heretofore been ad hoc in nature. In other words, the datapath elements in the prior art have not been defined in a way that allows a general tree-pattern matching between HDL statements and elements in a datapath cell library.
An associated problem or shortcoming of prior art datapath synthesizers is that they cannot synthesize datapaths using complex elements. In the prior art, the functionality of the library cells is limited to a single operation and a single output. However, many circuit elements in commercially useful cell libraries will have multiple outputs and perform complex functions.
Another related problem associated with prior art datapath synthesizers is that they cannot derive operations that do not have a direct mapping to elements in the datapath library. The present invention provides a set of general rules for mapping elements that are not explicitly defined in the datapath library.
Still another problem associated with prior art datapath synthesizers is that they fail to merge complex multi-output circuit elements in an optimal manner.